The present invention relates to a semiconductor device which has a stress insulating film on a gate electrode and to a fabrication method of such a semiconductor device.
A conventional semiconductor device which has a stress insulating film on a gate electrode with the view of improving the drivability of transistors has been proposed (see, for example, Japanese Laid-Open Patent Publication No. 2003-60076). Hereinafter, the conventional semiconductor device is described with reference to FIG. 17. FIG. 17 is a cross-sectional view of the structure of the conventional semiconductor device.
As shown in FIG. 17, a semiconductor substrate 700 made of silicon includes an isolation region 701 between an N-type MOS formation region N and a P-type MOS formation region P. In such a structure, the N-type MOS formation region includes an active region 700a which is part of the semiconductor substrate 700 surrounded by the isolation region 701, while the P-type MOS formation region includes an active region 700b which is another part of the semiconductor substrate 700 surrounded by the isolation region 701. A gate electrode 704a made of a conductive film is provided on the active region 700a of the N-type MOS formation region with a gate insulating film 703a made of an insulating film interposed therebetween. A gate electrode 704b made of a conductive film is provided on the active region 700b of the P-type MOS formation region with a gate insulating film 703b made of an insulating film interposed therebetween. The side faces of the gate electrodes 704a and 704b are covered with side walls 706a and 706b made of an insulating film.
The part of the active region 700a of the N-type MOS formation region diagonally under the gate electrode 704a is an N-type extension region 705a. The part of the active region 700a diagonally under the side wall 706a is an N-type source-drain region 707a. The part of the active region 700b of the P-type MOS formation region diagonally under the gate electrode 704b is a P-type extension region 705b. The part of the active region 700b diagonally under the side wall 706b is a P-type source-drain region 707b. Silicide films 708a and 708b are provided on the source-drain regions 707a and 707b, respectively. Silicide films 709a and 709b are provided on the gate electrodes 704a and 704b, respectively.
In the N-type MOS formation region, a tensile stressor insulating film 710 made of a silicon nitride film is provided on the semiconductor substrate 700 so as to cover the gate electrode 704a. On the other hand, in the P-type MOS formation region, a compressive stressor insulating film 711 made of a silicon nitride film is provided on the semiconductor substrate 700 so as to cover the gate electrode 704b. An interlayer insulating film 712 is provided on the stress insulating films 710 and 711.
According to the conventional semiconductor device, due to the tensile stressor insulating film 710 covering the gate electrode 704a, tensile stress acts on a channel of an N-type MOS transistor (i.e., a channel in the semiconductor substrate 700 which exists under the gate electrode 704a) in both gate length direction and gate width direction. On the other hand, due to the compressive stressor insulating film 711 covering the gate electrode 704b, compressive stress acts on a channel of a P-type MOS transistor (i.e., a channel in the semiconductor substrate 700 which exists under the gate electrode 704b) in both gate length direction and gate width direction.
However, the conventional semiconductor device is accompanied by the problems described below.
Herein, to improve the drivability of a MIS (Metal-Insulator-Semiconductor) transistor, the stress applied to the MIS transistor is directional. The orientation (tensile or compressive) and size of the stress applied to the channel of the MIS transistor are described below with reference to FIGS. 18A and 18B. FIG. 18A is a perspective view which illustrates the orientation and size of stress with which the drivability of N-type and P-type MIS transistors is improved where the gate length direction of the gate electrodes of the N-type and P-type MIS transistors is set to <110> direction. FIG. 18B is a perspective view which illustrates the orientation and size of stress with which the drivability of N-type and P-type MIS transistors is improved where the gate length direction of the gate electrodes of the N-type and P-type MIS transistors is set to <100> direction.
In the case where gate electrodes 804a and 804b are provided on active regions 800a and 800b which are the parts of a semiconductor substrate surrounded by an isolation region such that the gate length direction of the gate electrodes 804a and 804b is <110> direction as shown in FIG. 18A, it is necessary for improvement in drivability of the N-type MIS transistor to cause both tensile stress in the gate length direction and tensile stress in the gate width direction on the channel of the N-type MIS transistor. As for vertical stress from the gate electrode side with respect to the channel, compressive stress is effective.
On the other hand, to improve the drivability of the P-type MIS transistor, it is necessary to cause both compressive stress in the gate length direction and tensile stress in the gate width direction on the channel of the P-type MIS transistor.
In the case where gate electrodes 904a and 904b are provided on active regions 900a and 900b which are the parts of a semiconductor substrate surrounded by an isolation region such that the gate length direction of the gate electrodes 904a and 904b is <100> direction as shown in FIG. 18B, it is necessary for improvement in drivability of the N-type MIS transistor to cause both tensile stress in the gate length direction and compressive stress in the gate width direction on the channel of the N-type MIS transistor. As for vertical stress from the gate electrode side with respect to the channel, compressive stress is effective.
On the other hand, to improve the drivability of the P-type MIS transistor, it is necessary to cause compressive stress in the gate length direction on the channel of the P-type MIS transistor. (It should be noted that, as for the gate width direction, no matter which of compressive stress or tensile stress is applied, the applied stress rarely affects the characteristics of the P-type MIS transistor.
Thus, to improve the drivability of the MIS transistors, the stress applied to the channel of the MIS transistors is directional.
In the case where, however, in the conventional semiconductor device, the gate length direction of the gate electrodes of the N-type and P-type MOS transistors is set to <110> direction, the above-described directional stress causes the problems described below.
In the N-type MOS transistor, referring to FIG. 17, the tensile stressor insulating film 710 covering the gate electrode 704a produces tensile stress in both gate length direction and gate width direction on the channel of the N-type MOS transistor, so that the drivability of the N-type MOS transistor is improved. However, although it is desirable in the P-type MOS transistor that compressive stress is caused in the gate length direction while tensile stress is caused in the gate width direction on the channel of the P-type MOS transistor (see FIG. 18A), the compressive stressor insulating film 711 covering the gate electrode 704b as shown in FIG. 17 causes compressive stress on the channel of the P-type MOS transistor not only in the gate length direction but also in the gate width direction, resulting in deterioration in drivability of the P-type MOS transistor.
In the case where, on the other hand, in the conventional semiconductor device, the gate length direction of the gate electrodes of the N-type and P-type MOS transistors is set to <100> direction, the above-described directional stress causes the problems described below.
In the P-type MOS transistor, referring to FIG. 17, the compressive stressor insulating film 711 covering the gate electrode 704b produces compressive stress on the channel of the P-type MOS transistor in the gate length direction, so that the drivability of the P-type MOS transistor is improved. However, although it is desirable in the N-type MOS transistor that tensile stress is caused in the gate length direction while compressive stress is caused in the gate width direction on the channel of the N-type MOS transistor (see FIG. 18B), the tensile stressor insulating film 710 covering the gate electrode 704a as shown in FIG. 17 causes tensile stress on the channel of the N-type MOS transistor not only in the gate length direction but also in the gate width direction, resulting in deterioration in drivability of the N-type MOS transistor.
As described above, the conventional semiconductor device has the stress insulating film 710 or 711 on all of the upper faces, side faces facing in the gate length direction, and side faces facing in the gate width direction of the gate electrodes 704a and 704b as shown in FIG. 17. In the case where the orientation of stress with which the drivability of a MIS transistor is improved differs between the gate length direction and the gate width direction, any one of the stress caused in the gate length direction and the stress caused in the gate width direction has such an orientation that the drivability of the MIS transistor is deteriorated. Therefore, the drivability of the MIS transistor is deteriorated.